Current Program Status Register

The Linux/ARM embedded platform

Jason D. Bakos , in Embedded Systems, 2016

1.5.two Status register

ARM v6/v7 maintains a status register chosen the CPSR (current program status register) that holds four status bits, negative (N), zippo (Z), carry (C), and overflow (O). These bits tin exist used for conditional execution of subsequent instructions.

The bits are set co-ordinate to the virtually recently executed ALU didactics that includes the special "south" suffix. For example, the " adds " teaching will modify the condition bits but the " add " instruction will not.

Most all ARM instructions can include an optional status lawmaking that determines if the instruction will be executed or skipped over. In other words, an teaching whose status code is evaluated to false will not change the state of the processor, such equally writing a result register to changing the PC.

For example, the ldreq education will only execute if the Z-scrap in the CPSR is set, which will exist the case if the near recent computational instruction resulted in a result of naught.

For case, the sequence:

subs r2,r2,#1

streq r3, [r0]

…will decrement register r2 and store r3 only if the new value of r2 is zero.

The compare (cmp) educational activity tin be used to set the status $.25 without any other side effect.

For example:

cmp r2,r3

streq r4, [r0]

…will store register r4 only if the contents of registers r2 and r3 are equal.

When combining the status lawmaking and the "s" suffix, the status code comes outset, for example,

addeqs r0,r0,r1

The complete list of conditional suffixes are shown in Table ane.1.

Table 1.1. Condition Codes

Suffix Flags Meaning
eq z set Equal
ne z clear Not equal
hs c set Unsigned   >   =
lo c clear Unsigned <
mi n ready Negative
pl n articulate Positive or zero
vs v set Overflow
vc v clear No overflow
hi c set and z articulate Unsigned >
ls c clear and z set Unsigned   <   =
ge n and v the same Signed   >   =
lt n and v dissimilar Signed <
gt z clear, or n and v the aforementioned Signed >
le z fix, or northward and five different Signed   <   =

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ARM PROCESSOR FUNDAMENTALS

ANDREW N. SLOSS , ... CHRIS WRIGHT , in ARM System Developer'south Guide, 2004

two.2.i PROCESSOR MODES

The processor fashion determines which registers are active and the access rights to the cpsr annals itself. Each processor manner is either privileged or nonprivileged: A privileged style allows total read-write access to the cpsr. Conversely, a nonprivileged fashion only allows read access to the control field in the cpsr only still allows read-write access to the status flags.

In that location are vii processor modes in total: six privileged modes (abort, fast interrupt request, interrupt request, supervisor, system, and undefined) and one nonprivileged way (user).

The processor enters abort mode when there is a failed try to access retentiveness. Fast interrupt request and interrupt request modes correspond to the ii interrupt levels bachelor on the ARM processor. Supervisor mode is the style that the processor is in after reset and is mostly the fashion that an operating arrangement kernel operates in. System manner is a special version of user mode that allows full read-write access to the cpsr. Undefined style is used when the processor encounters an instruction that is undefined or not supported by the implementation. User way is used for programs and applications.

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Architecture

Sarah L. Harris , David Money Harris , in Digital Design and Estimator Architecture, 2016

Exception Treatment

Now that we accept defined execution modes, exception vectors, and banked registers, we can define what occurs during an exception. Upon detecting an exception, the processor:

1.

Stores the CPSR into the banked SPSR

2.

Sets the execution mode and privilege level based on the type of exception

3.

Sets interrupt mask bits in the CPSR so that the exception handler will not be interrupted

four.

Stores the return address into the banked LR

v.

Branches to the exception vector table based on the blazon of exception

The processor then executes the educational activity in the exception vector table, typically a branch to the exception handler. The handler usually pushes other registers onto its stack, takes care of the exception, and pops the registers back off the stack. The exception handler returns using the MOVS PC, LR education, a special season of MOV that performs the following cleanup:

1.

Copies the banked SPSR to the CPSR to restore the status register

2.

Copies the banked LR (maybe adjusted for certain exceptions) to the PC to return to the programme where the exception occurred

three.

Restores the execution mode and privilege level

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Porting Applications from the ARM7 to the Cortex-M3

Joseph Yiu , in The Definitive Guide to the ARM Cortex-M3 (2d Edition), 2010

18.two.2 Interrupts

The second target is the deviation in the interrupt controller being used. Program lawmaking to control the interrupt controller, such equally enabling or disabling interrupts, volition need to be inverse. In addition, new code is required for setting up interrupt priority levels and vector addresses for various interrupts.

The interrupt return method is also changed. This requires modification of interrupt return in assembler code or, if C language is used, it might be necessary to brand adjustments on compile directives.

Enable and disable of interrupts, previously done by modifying Electric current Program Status annals (CPSR), must be replaced by setting up the Interrupt Mask register. In addition, in the ARM7TDMI, it is possible to reenable interrupt at the aforementioned time as interrupt return due to restore of CPSR from Saved Programme Status register (SPSR). In the Cortex-M3, if interrupts are disabled during an interrupt handler past setting PRIMASK, the PRIMASK should exist cleared manually before interrupt return. Otherwise, the interrupts will remain disabled.

In the Cortex-M3, some registers are automatically saved by the stacking and unstacking mechanisms. Therefore, some of the software stacking operations could be reduced or removed. However, in the instance of the Fast Interrupt request (FIQ) handler, traditional ARM cores have separate registers for FIQ (R8–R11). Those registers can be used past the FIQ without the need to push them into the stack. Nevertheless, in the Cortex-M3, these registers are not stacked automatically, so when an FIQ handler is ported to the Cortex-M3, either the registers being used past the handler must be changed or a stacking stride will be needed.

Code for nested interrupt handling tin can be removed. In the Cortex-M3, the NVIC has built-in nested interrupt treatment.

There are also differences in mistake handling. The Cortex-M3 provides various fault condition registers so that the cause of faults can be located. In add-on, new fault types are defined in the Cortex-M3 (due east.chiliad., stacking and unstacking faults, retentiveness direction faults, and difficult faults). Therefore, fault handlers will demand to be rewritten.

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Instruction Sets

Marilyn Wolf , in Computers equally Components (Fourth Edition), 2017

2.3.2 Information operations

Arithmetic and logical operations in C are performed in variables. Variables are implemented as memory locations. Therefore, to be able to write instructions to perform C expressions and assignments, we must consider both arithmetic and logical instructions too as instructions for reading and writing retention.

Fig. ii.viii shows a sample fragment of C lawmaking with information declarations and several assignment statements. The variables a, b, c, 10, y, and z all get data locations in memory. In most cases data are kept relatively separate from instructions in the program's memory image.

Figure ii.8. A C fragment with data operations.

ARM programming model

In the ARM processor, arithmetics and logical operations cannot exist performed directly on retention locations. While some processors allow such operations to directly reference main memory, ARM is a load-store compages—data operands must first exist loaded into the CPU and then stored back to chief memory to save the results. Fig. 2.nine shows the registers in the bones ARM programming model. ARM has xvi general-purpose registers, r0 through r15. Except for r15, they are identical—any performance that tin can be done on one of them can be done on the others. The r15 register has the same capabilities every bit the other registers, but it is also used as the program counter. The program counter should of course not exist overwritten for employ in data operations. However, giving the PC the properties of a general-purpose register allows the program counter value to be used as an operand in computations, which tin can make certain programming tasks easier.

Figure 2.nine. The basic ARM programming model.

The other of import basic register in the programming model is the current program status annals (CPSR). This register is set automatically during every arithmetic, logical, or shifting performance. The meridian four bits of the CPSR concur the post-obit useful data nigh the results of that arithmetics/logical performance:

•

The negative (Due north) chip is set when the result is negative in two's-complement arithmetic.

•

The cipher (Z) bit is set when every bit of the result is zero.

•

The carry (C) bit is set when in that location is a deport out of the operation.

•

The overflow (5) fleck is fix when an arithmetic functioning results in an overflow.

These bits can be used to easily check the results of an arithmetics operation. However, if a concatenation of arithmetics or logical operations is performed and the intermediate states of the CPSR bits are important, they must be checked at each step because the adjacent operation changes the CPSR values.

Example 2.1 illustrates the computation of CPSR $.25.

Instance two.1 Condition Bit Ciphering in the ARM

An ARM word is 32 bits. In C notation, a hexadecimal number starts with 0x, such as 0xffffffff, which is a ii'south-complement representation of −one in a 32-scrap give-and-take.

Here are some sample calculations:

•

−1  + 1  = 0: Written in 32-chip format, this becomes 0xffffffff   +   0x1   =   0x0, giving the CPSR value of NZCV   =   1001.

•

0  − 1  =   −1: 0x0   −   0x1   =   0xffffffff, with NZCV   =   1000.

•

2 31   − 1  + 1  =   −2 31 : 0x7fffffff   +   0x1   =   0x80000000, with NZCV   =   0101.

The basic form of a data didactics is simple:

      ADD r0,r1,r2

This instruction sets annals r0 to the sum of the values stored in r1 and r2. In add-on to specifying registers as sources for operands, instructions may also provide firsthand operands, which encode a constant value directly in the pedagogy. For case,

      Add r0,r1,#2

      Sets r0 to r1 + 2.

The major data operations are summarized in Fig. 2.10. The arithmetic operations perform addition and subtraction; the with-comport versions include the current value of the carry chip in the computation. RSB performs a subtraction with the guild of the two operands reversed, so that RSB r0,r1,r2 sets r0 to exist r2   −   r1. The bit-wise logical operations perform logical AND, OR, and XOR operations (the exclusive-or is called EOR). The BIC educational activity stands for bit clear: BIC r0,r1,r2 sets r0 to r1 and not r2. This instruction uses the second source operand as a mask: Where a chip in the mask is 1, the corresponding chip in the get-go source operand is cleared. The MUL didactics multiplies 2 values, merely with some restrictions: No operand may be an firsthand, and the 2 source operands must be different registers. The MLA pedagogy performs a multiply-accumulate performance, particularly useful in matrix operations and point processing. The instruction MLA   r0,r1,r2,r3 sets r0 to the value r1 × r2 + r3.

Figure 2.10. ARM data instructions.

The shift operations are not dissever instructions—rather, shifts can be practical to arithmetics and logical instructions. The shift modifier is always practical to the second source operand. A left shift moves $.25 up toward the near-pregnant $.25, while a right shift moves bits downwardly to the to the lowest degree-significant bit in the word. The LSL and LSR modifiers perform left and right logical shifts, filling the least-significant bits of the operand with zeroes. The arithmetics shift left is equivalent to an LSL, but the ASR copies the sign scrap—if the sign is 0, a 0 is copied, while if the sign is ane, a 1 is copied. The rotate modifiers always rotate right, moving the bits that fall off the least-significant bit up to the virtually-significant bit in the discussion. The RRX modifier performs a 33-flake rotate, with the CPSR's C fleck being inserted above the sign bit of the word; this allows the carry flake to be included in the rotation.

The instructions in Fig. two.11 are comparison operands—they exercise not modify general-purpose registers but only set the values of the NZCV bits of the CPSR register. The compare instruction CMP r0, r1 computes r0   −   r1, sets the status bits, and throws away the result of the subtraction. CMN uses an addition to prepare the status bits. TST performs a bit-wise AND on the operands, while TEQ performs an sectional-or.

Figure 2.11. ARM compare instructions.

Fig. 2.12 summarizes the ARM move instructions. The educational activity MOV r0,r1 sets the value of r0 to the current value of r1. The MVN instruction complements the operand bits (one's complement) during the move.

Figure 2.12. ARM move instructions.

Values are transferred betwixt registers and retention using the load-store instructions summarized in Fig. 2.13. LDRB and STRB load and store bytes rather than whole words, while LDRH and SDRH operate on one-half-words and LDRSH extends the sign bit on loading. An ARM accost may be 32 bits long. The ARM load and store instructions exercise not direct refer to principal memory addresses, considering a 32-scrap address would not fit into an instruction that included an opcode and operands. Instead, the ARM uses annals-indirect addressing. In register-indirect addressing, the value stored in the register is used as the address to be fetched from retentiveness; the effect of that fetch is the desired operand value. Thus, every bit illustrated in Fig. ii.xiv, if we set r1  =   0x100, the instruction

Figure 2.xiii. ARM load-store instructions and pseudo-operations.

Effigy 2.fourteen. Register-indirect addressing in the ARM.

      LDR r0,[r1]

sets r0 to the value of memory location 0x100. Similarly, STR   r0,   [r1] would store the contents of r0 in the memory location whose accost is given in r1. There are several possible variations:

      LDR r0,[r1, -r2]

loads r0 from the accost given by r1 − r2, while

      LDR r0,[r1, #4]

loads r0 from the address r1   +   4.

This begs the question of how we get an address into a annals—nosotros demand to be able to set a register to an arbitrary 32-scrap value. In the ARM, the standard way to set a register to an accost is past performing arithmetics on a annals. Ane option for the register to employ for this operation is the program counter. By adding or subtracting to the PC a constant equal to the distance between the current didactics (ie, the instruction that is computing the address) and the desired location, we can generate the desired address without performing a load. The ARM programming arrangement provides an ADR pseudo-operation to simplify this step. Thus, as shown in Fig. ii.15, if nosotros requite location 0x100 the name FOO, we can utilize the pseudo-operation

Figure two.fifteen. Calculating an absolute address using the PC.

      ADR r1,FOO

to perform the same role of loading r1 with the address 0x100. Some other technique is used in high-level languages such every bit C. As we will come across when we talk over procedure calls, languages utilise a mechanism called a frame to pass parameters betwixt functions. For the moment, a simplified view of the process is sufficient. A register holds a frame pointer (fp) that points to the elevation of the frame; elements inside the frame are accessed using offsets from fp. The assembler syntax [fp,#-n] is used to take the due northth location from fp.

Example 2.2 illustrates how to implement C assignments in ARM instruction.

Example 2.2 C Assignments in ARM Instructions

Nosotros volition utilise the assignments of Fig. two.8. The semicolon (;) begins a comment later an didactics, which continues to the end of that line. The argument

      ten = (a + b) - c;

can exist implemented past using r0 for a, r1 for b, r2 for c, and r3 for x. We also need registers for indirect addressing. In this case, we will reuse the aforementioned indirect addressing annals, r4, for each variable load. The lawmaking must load the values of a, b, and c into these registers before performing the arithmetic, and it must store the value of x dorsum to retentivity when it is done.

Hither is the code generated by the gcc compiler for this argument. It uses a frame pointer to hold the variables: a is at −24, b at −28, c at −32, and x at −36:

      ldr r2, [fp, #-24]

      ldr r3, [fp, #-28]

      add together r2, r2, r3

      ldr r3, [fp, #-32]

      rsb r3, r3, r2

      str r3, [fp, #-36]

The operation

      y = a∗(b + c);

can be coded similarly, but in this instance we will reuse more registers by using r0 for both a and b, r1 for c, and r2 for y. Again, nosotros volition apply r4 to store addresses for indirect addressing. The resulting lawmaking from gcc looks similar this:

      ldr r2, [fp, #-28]

      ldr r3, [fp, #-32]

      add r2, r2, r3

      ldr r3, [fp, #-24]

      mul r3, r2, r3

      str r3, [fp, #-40]

The C argument

      z = (a << ii) | (b & xv);

results in this gcc-generated code:

      ldr r3, [fp, #-24]

      mov r2, r3, asl #2

      ldr r3, [fp, #-28]

      and r3, r3, #fifteen

      orr r3, r2, r3

      str r3, [fp, #-44]

More addressing modes

We have already seen three addressing modes: register, immediate, and indirect. The ARM as well supports several forms of base-plus-offset addressing, which is related to indirect addressing. But rather than using a annals value direct as an accost, the register value is added to another value to form the address. For example,

      LDR r0,[r1,#16]

loads r0 with the value stored at location r1   +   sixteen. Hither, r1 is referred to as the base of operations and the immediate value the offset. When the offset is an immediate, information technology may take any value upwards to 4096; another annals may also be used equally the offset. This addressing mode has two other variations: autoindexing and postindexing. Autoindexing updates the base register, such that

      LDR r0,[r1,#16]!

first adds 16 to the value of r1 and and so uses that new value as the accost. The ! operator causes the base register to exist updated with the computed address then that it tin can be used again later. Our examples of base-plus-offset and autoindexing instructions volition fetch from the same memory location, but autoindexing will likewise alter the value of the base of operations annals r1. Postindexing does non perform the offset calculation until later on the fetch has been performed. Consequently,

      LDR r0,[r1],#16

will load r0 with the value stored at the retentiveness location, whose address is given by r1, and then add xvi to r1 and set r1 to the new value. In this instance, the postindexed manner fetches a different value than the other two examples just ends upward with the same final value for r1 every bit does autoindexing.

We have used the ADR pseudo-op to load addresses into registers to access variables because this leads to uncomplicated, easy-to-read code (at least by associates language standards). Compilers tend to utilize other techniques to generate addresses, considering they must deal with global variables and automated variables.

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