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What Registers Can U Use With Real Mode 16 Bit

Written By Monday 13 June 2022 Add Comment Edit
Microprocessor modes for the x86 architecture
  • Existent mode (Intel 8086)
  • 8080 emulation manner (NEC V20/V30 merely)
  • Protected mode (Intel 80286)
  • Virtual 8086 mode (Intel 80386)
  • Unreal way (Intel 80386)
  • System Management Mode (Intel 386SL)
  • Long manner (AMD Opteron)
  • x86 virtualization (AMD Athlon 64)
First supported platform shown in parentheses

In computing, protected mode, also chosen protected virtual address mode, [i] is an operational mode of x86-compatible central processing units (CPU). Information technology allows system software to use features such every bit virtual memory, paging and safe multi-tasking designed to increase an operating system'southward control over application software. [2] [3]

When a processor that supports x86 protected mode is powered on, it begins executing instructions in real mode, in order to maintain backwards compatibility with earlier x86 processors. [4] Protected mode may only exist entered later the system software sets upwardly several descriptor tables and enables the Protection Enable (PE) flake in the command register 0 (CR0). [5]

Protected mode was beginning added to the x86 compages in 1982, [six] with the release of Intel's 80286 (286) processor, and after extended with the release of the 80386 (386) in 1985. [seven] Due to the enhancements added by protected manner, information technology has go widely adopted and has become the foundation for all subsequent enhancements to the x86 compages. [viii]

Contents

  • 1 History
    • 1.1 The 286
    • 1.2 The 386
  • 2 386 additions to protected way
  • 3 Inbound and exiting protected mode
  • 4 Features
    • iv.1 Privilege levels
    • iv.2 Real mode application compatibility
    • four.3 Virtual 8086 mode
    • 4.4 Segment addressing
      • 4.4.one Protected mode
      • iv.four.ii 286
      • 4.iv.iii 386
      • iv.4.4 Structure of segment descriptor entry
    • 4.5 Paging
    • iv.6 Multitasking
  • 5 Operating systems
  • six See besides
  • vii References
  • 8 External links

History

The Intel 8086, the predecessor to the 286, was originally designed with a 20-bit address double-decker for its retentiveness. [9] This immune the processor to access twoxx bytes of retention, equivalent to one megabyte. [9] At the time, 1 megabyte was considered a relatively large corporeality of memory, [10] so the designers of the IBM Personal Calculator reserved the starting time 640 kilobytes for utilise past applications and the operating organisation and the remaining 384 kilobytes for the BIOS (Basic Input/Output System) and memory for add together-on devices. [xi]

As the cost of memory decreased and retentiveness use increased, the 1 MB limitation became a significant problem. Intel intended to solve this limitation along with others with the release of the 286. [xi]

The 286

For more details on this topic, see Intel 80286.

The initial protected mode, released with the 286, was non widely used. [xi] Several shortcomings such as the disability to access the BIOS or DOS calls due to inability to switch dorsum to real mode without resetting the processor prevented widespread usage. [12] Acceptance was additionally hampered by the fact that the 286 merely allowed memory access in 16 bit segments via each of four segment registers, meaning only four*twoxvi bytes, equivalent to 256 kilobytes, could be accessed at a time. [xi]

The 286 maintained backwards compatibility with the previous 8086 past initially entering real mode on power up. [4] Existent mode functioned almost identically to the 8086, assuasive older software to run unmodified on the newer 286. To access the extended functionality of the 286, the operating system would set the processor into protected mode. This enabled 24 bit addressing which allowed the processor to access 224 bytes of memory, equivalent to 16 megabytes. [9]

The 386

An Intel 80386 microprocessor

For more details on this topic, see Intel 80386.

With the release of the 386 in 1985, [seven] many of the bug preventing widespread adoption of the previous protected way were addressed. [xi] The 386 was released with an accost passenger vehicle size of 32 bits, which allows for 232 bytes of retentivity accessing, equivalent to 4 gigabytes. [13] The segment sizes were likewise increased to 32 $.25, meaning that the full address space of four gigabytes could be accessed without the need to switch betwixt multiple segments. [13] In addition to the increased size of the address jitney and segment registers, many other new features were added with the intention of increasing operational security and stability. [14] Protected mode is now used in virtually all modernistic operating systems which run on the x86 compages, such as Microsoft Windows, Linux, and many others. [15]

386 additions to protected manner

With the release of the 386, the following additional features were added to protected mode: [2]

  • Paging
  • 32-bit concrete and virtual address infinite (The 32-bit concrete address space is not nowadays on the 80386SX, and other 386 processor variants which use the older 286 bus. [16] )
  • 32-bit segment offsets
  • Ability to switch back to existent mode without resetting
  • Virtual 8086 mode

Entering and exiting protected mode

Until the release of the 386, protected way did non offer a straight method to switch back into existent mode once protected mode was entered. IBM devised a workaround (implemented in the IBM AT) which involved resetting the CPU via the keyboard controller and saving the organisation registers, stack arrow and oftentimes the interrupt mask in the real-time clock fleck's RAM. This allowed the BIOS to restore the CPU to a similar state and begin executing code before the reset.[ clarification needed ] Later, a triple fault was used to reset the 286 CPU, which was a lot faster and cleaner than the keyboard controller method (and does non depend on IBM AT-compatible hardware, but volition work on whatever 80286 CPU in any system). To enter protected style, the Global Descriptor Table (GDT) must first be created with a minimum of three entries: a null descriptor, a code segment descriptor and data segment descriptor. In an IBM-compatible car, the A20 line (21st accost line) also must be enabled to allow the use of all the address lines so that the CPU can access across one megabyte of memory (Merely the kickoff 20 are allowed to exist used after power-upward, to guarantee compatibility with older software written for the Intel 8088-based IBM PC and PC/XT models). After performing those two steps, the PE fleck must exist set in the CR0 register and a far bound must be fabricated to articulate the prefetch input queue.

            ; set PE bit            mov            eax            ,            cr0            or            eax            ,            1            mov            cr0            ,            eax            ; far spring (cs = selector of code segment)            jmp            cs            :@pm @pm:            ; Now we are in PM.

With the release of the 386, protected fashion could be exited by loading the segment registers with existent style values, disabling the A20 line and immigration the PE bit in the CR0 register, without the demand to perform the initial setup steps required with the 286.

Features

Protected mode has a number of features designed to heighten an operating system'due south command over application software, in order to increment security and system stability. [iii] These additions allow the operating arrangement to function in a way that would be significantly more difficult or even incommunicable without proper hardware support. [17]

Privilege levels

Example of privilege band usage in an operating system using all rings

In protected style, at that place are four privilege levels or rings, numbered from 0 to three, with ring 0 beingness the well-nigh privileged and 3 beingness the least. The apply of rings allows for system software to restrict tasks from accessing data, call gates or executing privileged instructions. [18] In near environments, the operating system and some device drivers run in band 0 and applications run in ring 3. [xviii]

Real way application compatibility

According to the Intel 80286 Developer'south Reference Manual, [nineteen]

" ...the 80286 remains upwardly compatible with well-nigh 8086 and 80186 application programs. Nigh 8086 applications programs can be re-compiled or re-assembled and executed on the 80286 in Protected Mode. "

For the virtually part, the binary compatibility with existent-fashion lawmaking, the ability to access up to 16 MB of physical retention, and ane GB of virtual memory, were the most apparent changes to application programmers. [nineteen] This was not without its limitations, if an application utilized or relied on any of the techniques beneath information technology wouldn't run: [20]

  • Segment arithmetic
  • Privileged instructions
  • Direct hardware access
  • Writing to a lawmaking segment
  • Executing information
  • Overlapping segments
  • Use of BIOS functions, due to the BIOS interrupts being reserved by Intel [21]

In reality, almost all DOS application programs violated these rules. [22] Due to these limitations, virtual 8086 mode was created and released with the 386. Despite such potential setbacks, Windows three.0 and its successors can take advantage of the binary compatibility with real mode to run many Windows two.x (Windows two.0 and Windows 2.1x) applications, which run in existent mode in Windows 2.x, in protected manner. [23]

Virtual 8086 mode

Principal commodity: Virtual 8086 mode

With the release of the 386, protected mode offers what the Intel manuals phone call virtual 8086 mode. Virtual 8086 mode is designed to allow lawmaking previously written for the 8086 to run unmodified and meantime with other tasks, without compromising security or system stability. [24] Virtual 8086 manner, notwithstanding, is not completely backwards compatible with all programs. Programs that crave segment manipulation, privileged instructions, straight hardware admission, or utilise cocky-modifying code volition generate an exception that must be served by the operating system. [25] In improver, applications running in virtual 8086 mode generate a trap with the utilise of instructions that involve input/output (I/O), which can negatively touch functioning. [26] Due to these limitations, some programs originally designed to run on the 8086 cannot be run in virtual 8086 way. As a consequence, system software is forced to either compromise organisation security or backwards compatibility when dealing with legacy software. An example of such a compromise tin exist seen with the release of Windows NT, which dropped backwards compatibility for "ill-behaved" DOS applications. [27]

Segment addressing

virtual segments of 80286

For more details on this topic, see X86 retentiveness segmentation.

In real fashion each logical accost points direct into physical retentivity location, every logical address consists of 2 sixteen bit parts: The segment part of the logical accost contains the base address of a segment with a granularity of 16 bytes, i.e. a segments may start at concrete address 0, 16, 32, ..., 220-xvi. The beginning part of the logical address contains an kickoff within the segment, i.e. the physical address tin be calculated as physical_address : = segment_part × sixteen + start (if the address line A20 is enabled), respectively (segment_part × 16 + first) mod twotwenty (if A20 is off)[ description needed ] Every segment has a size of iisixteen bytes.

Protected fashion

In protected mode the segment_part is replaced by a 16 bit selector, the 13 upper bits (bit 3 to bit fifteen) of the selector contains the index of an entry inside a descriptor table. The next bit (bit ii) specifies if the operation is used with the GDT or the LDT. The lowest 2 $.25 (scrap 1 and bit 0) of the selector are combined to ascertain the privilege of the request; where a value of 0 has the highest priority and value of 3 is the everyman.

The descriptor tabular array entry defines:

  • the real linear address of the segment
  • a limit value for the segment size
  • some attribute bits (flags)

286

The segment address inside the descriptor table entry has a length of 24 bits so every byte of the physical memory can be defined as leap of the segment. The limit value inside the descriptor tabular array entry has a length of sixteen $.25 so segment length tin can be betwixt i byte and twosixteen byte. The calculated linear accost equals the concrete retentiveness address.

386

The segment address inside the descriptor table entry is expanded to 32 bits and then every byte of the physical memory tin can be divers every bit spring of the segment. The limit value inside the descriptor table entry is expanded to twenty bits and completed with a granularity flag (Thou-bit, for curt):

  • If G-chip is zero limit has a granularity of one byte, i.e. segment size may exist 1, 2, ..., 220 bytes.
  • If G-bit is one limit has a granularity of 212 bytes, i.e. segment size may exist 1 × 212, 2 × 212, ..., 220 × 212 bytes. If paging is off, the calculated linear accost equals the physical memory address. If paging is on, the calculated linear accost is used as input of paging.

The 386 processor also uses 32 bit values for the address offset.

For maintaining compatibility with 286 protected style a new default flag (D-scrap, for short) was added. If the D-scrap of a code segment is off (0) all commands inside this segment will exist interpreted as 16-bit commands by default; if it is on (1), they will be interpreted as 32-chip commands.

Construction of segment descriptor entry

B $.25 80286 80386 B
0 00..07,0..seven limit bits 0..15 of limit 0
i 08..15,0..7 1
2 xvi..23,0..seven base accost $.25 0..23 of base of operations address ii
3 24..31,0..7 3
4 32..39,0..7 4
5 twoscore..47,0..vii aspect flags #1 5
half-dozen 48..51,0..three unused bits 16..19 of limit half-dozen
52..55,4..seven aspect flags #2
vii 56..63,0..7 bits 24..31 of base accost seven
Columns B
Byte commencement inside entry
Column bits, beginning range
Bit offset inside entry
Cavalcade $.25, second range
Fleck start inside byte
attribute flags #2
52 4 unused, available for operating organisation
53 5 reserved, should be zero
54 6 default flag / D-bit
55 7 granularity flag / G-scrap

Paging

Common method of using paging to create a virtual address space

paging (intel 80386) with page size of 4K

For more details on this topic, see Paging.

In addition to adding virtual 8086 mode, the 386 also added paging to protected manner. [28] Through paging, system software tin can restrict and command a chore's access to pages, which are sections of memory. In many operating systems, paging is used to create an contained virtual address infinite for each chore. This prevents one task from manipulating the memory of another. Paging also allows for pages to be moved out of primary storage and onto a slower and larger secondary storage, such as a hard disk. [29] This allows for more retentiveness to be used than physically bachelor in primary storage. [29] The x86 compages allows control of pages through two arrays: page directories and page tables. Originally, a folio directory was the size of i page, 4 kilobytes, and contained 1,024 page directory entries (PDE), although subsequent enhancements to the x86 compages have added the ability to use larger page sizes. Each PDE independent a arrow to a page table. A page table was also originally 4 kilobytes in size and contained 1,024 page table entries (PTE). Each PTE contained a pointer to the bodily page's physical accost and are just used when 4 kilobyte pages are used. At any given time, only i page directory may exist in agile use. [xxx]

Multitasking

Through the use of the rings, privileged call gates, and the Task Land Segment (TSS), introduced with the 286, preemptive multitasking was made possible on the x86 architecture. The TSS allows general-purpose registers, segment selector fields, and stacks to all exist modified without affecting those of another task. The TSS also allows a task's privilege level, and I/O port permissions to be independent of another chore's.

In many operating systems, the full features of the TSS are not used. [31] This is commonly due to portability concerns or due to the functioning issues created with hardware task switches. [31] Equally a effect many operating systems employ both hardware and software to create a multitasking system. [32]

Operating systems

Operating systems like OS/ii 1.x endeavor to switch the processor between protected and real modes. This is both tedious and dangerous, because a real mode programme can easily crash a computer. OS/2 i.x defines restrictive programming rules allowing a Family API or bound program to run in either real or protected mode. Some early Unix operating systems, Bone/2 ane.x, and Windows used this mode. Windows 3.0 was able to run real mode programs in 16-chip protected mode. Windows 3.0, when switching to protected mode, decided to preserve the single privilege level model that was used in real style, which is why Windows applications and DLLs tin claw interrupts and practise direct hardware access. That lasted through the Windows 9x series. If a Windows 1.10 or two.10 program is written properly and avoids segment arithmetic, information technology will run the same way in both real and protected modes. Windows programs more often than not avoid segment arithmetic because Windows implements a software virtual memory scheme, moving program code and data in retention when programs are non running, and then manipulating absolute addresses is unsafe; programs should simply proceed handles to memory blocks when non running. Starting an old program while Windows 3.0 is running in protected mode triggers a warning dialog, suggesting to either run Windows in existent mode or to obtain an updated version of the application. Updating well-behaved programs using the MARK utility with the Retentivity parameter avoids this dialog. Information technology is not possible to accept some GUI programs running in xvi-bit protected mode and other GUI programs running in real way. In Windows 3.1 existent way disappeared.

Today, 16-bit protected mode is still used for running applications, due east.g. DPMI uniform DOS extender programs (through virtual DOS machines) or Windows 3.x applications (through the Windows on Windows subsystem) and sure classes of device drivers (eastward.g. for changing the screen-resolution using BIOS functionality) in OS/2 two.0 and afterward, all under command of a 32-bit kernel.

See also

  • Assembly language
  • Intel
  • Ring (figurer security)
  • x86 associates language

References

  1. ^ "Memory access control method and organisation for realizing the aforementioned" (Patent). US Patent 5483646. May 23, 1995. Retrieved 2007-07-14. "The retentiveness admission command organization according to claim iv, wherein said first address mode is a real accost way, and said second address mode is a protected virtual address mode."
  2. ^ a b "ii.one.iii The Intel 386 Processor (1985)". Intel 64 and IA-32 Architectures Software Developer'southward Transmission. Denver, Colorado: Intel. May 2007. p. 35.
  3. ^ a b "Guide: What does protected style mean?" (Guide). Delorie software. July 14, 2007. Retrieved 2007-07-xiv. "The purpose of protected mode is not to protect your program. The purpose is to protect anybody else (including the operating organization) from your program."
  4. ^ a b "iii.2 Modes of Operation". Intel 65 and IA-32 Architectures Software Programmer's Manual. Denver, Colorado: Intel. May 2005. p. 59.
  5. ^ Collins, Robert (2007). "Protected Mode Basics" (PDF). ftp.utcluj.ro. Retrieved 2009-07-31.
  6. ^ "ii.1.two The Intel 286 Processor (1982)". Intel 64 and IA-32 Architectures Software Developer's Manual. Denver, Colorado: Intel. May 2007. p. 34.
  7. ^ a b "Intel Global Citizenship Written report 2003" (Timeline). Archived from the original on 2008-03-22. Retrieved 2007-07-xiv. "1985 Intel launches Intel386 processor"
  8. ^ "2.1 Brief History of the IA-32 Architecture". Intel 64 and IA-32 Architectures Software Developer's Manual. Denver, Colorado: Intel. May 2007. p. 31.
  9. ^ a b c "A+ - Hardware" (Tutorial/Guide). PC Microprocessor Developments and Features Tutorials. BrainBell.com. Retrieved 2007-07-24.
  10. ^ [David] (March 23, 2001). "A CPU History" (Article). PCMechanic. Archived from the original on 2008-01-fifteen. Retrieved 2007-07-24. "What is interesting is that the designers of the time never suspected anyone would ever need more than 1 MB of RAM."
  11. ^ a b c d e Kaplan, Yariv (1997). "Introduction to Protected-Way" (Article). Internals.com. Retrieved 2007-07-24.
  12. ^ [Scott] (March 24, 2006). "P2 (286) Second-Generation Processors". Upgrading and Repairing PCs, 17th Edition (Volume) (17 ed.). Que. ISBN 0-7897-3404-iv. Retrieved July 2007.
  13. ^ a b "two.1 Memory Organisation and Segmentation". Intel 80386 Programmer'southward Reference Transmission 1986 (Manual). Santa Clara, CA: Intel. 1986.
  14. ^ "3.1 Modes of Operation". Intel 64 and IA-32 Architectures Software Programmer's Manual. Denver, Colorado: Intel. May 2007. p. 55.
  15. ^ Hyde, Randall (November 2004). "12.10. Protected Mode Operation and Device Drivers". Write Nifty Code. O'Reilly. ISBN 1-59327-003-viii.
  16. ^ Shvets, Gennadiy (June three, 2007). "Intel 80386 processor family" (Article). Retrieved 2007-07-24. "80386SX — low cost version of the 80386. This processor had 16 bit external data bus and 24-flake external address bus."
  17. ^ "7 Multitasking". Intel 80386 Programmer's Reference Manual 1986 (Manual). Santa Clara, CA: Intel. 1986.
  18. ^ a b "6.3.five Calls to Other Privilege Levels". Intel 64 and IA-32 Architectures Software Developer's Manual. Denver, Colorado: Intel. May 2007. p. 162.
  19. ^ a b "1.two Modes of Operation". Intel 80286 Programmer's Reference Manual 1987 (Manual). Santa Clara, CA: Intel. 1987.
  20. ^ "Appendix C 8086/8088 Compatibility Considerations". Intel 80286 Programmer's Reference Manual 1987 (Manual). Santa Clara, CA: Intel. 1987.
  21. ^ "Memory access control method and system for realizing the same" (Patent). U.s. Patent 5483646. May 6, 1998. Retrieved 2007-07-25. "This has been impossible to-appointment and has forced BIOS development teams to add together support into the BIOS for 32 bit office calls from 32 bit applications."
  22. ^ Robinson, Tim (August 26, 2002). "Virtual 8086 Mode" (Guide). berliOS. Retrieved 2007-07-25. "...secondly, protected style was besides incompatible with the vast corporeality of real-mode lawmaking around at the fourth dimension."
  23. ^ Robinson, Tim (August 26, 2002). "Virtual 8086 Style" (Guide). berliOS. Retrieved 2007-07-25.
  24. ^ "15.2 Virtual 8086 Mode". Intel 64 and IA-32 Architectures Software Developer'south Transmission. Denver, Colorado: Intel. May 2007. p. 560.
  25. ^ "15.2.7 Sensitive Instructions". Intel 64 and IA-32 Architectures Software Programmer's Manual. Denver, Colorado: Intel. May 2007. p. 568.
  26. ^ Robinson, Tim (August 26, 2002). "Virtual 8086 Mode" (Guide). berliOS. Retrieved 2007-07-25. "A downside to using V86 mode is speed: every IOPL-sensitive didactics will crusade the CPU to trap to kernel fashion, equally will I/O to ports which are masked out in the TSS."
  27. ^ [Prasad]; Millind Borate (October 1999). Undocumented Windows NT (Book). Hungry Minds. ISBN 0-7645-4569-eight.
  28. ^ "ProtectedMode overview [deinmeister.de]" (Website). Retrieved 2007-07-29.
  29. ^ a b "What Is PAE X86?" (Article). Microsoft TechNet. May 28, 2003. Retrieved 2007-07-29. "The paging procedure allows the operating system to overcome the real physical memory limits. However, it besides has a direct bear upon on performance considering of the fourth dimension necessary to write or recollect data from deejay."
  30. ^ Gareau, Jean. "Advanced Embedded x86 Programming: Paging" (Guide). Embedded.com. Retrieved 2007-07-29. "Only one page directory may be active at a time, indicated by the CR3 annals."
  31. ^ a b "news: Multitasking for x86 explained #1" (Article). NewOrer. NewOrder. May ii, 2004. Archived from the original on 2007-02-12. Retrieved 2007-07-29. "The reason why software task switching is so popular is that it can be faster than hardware job switching. Intel never really developed the hardware task switching, they implemented information technology, saw that it worked, and only left information technology there. Advances in multitasking using software have made this form of task switching faster (some say upwardly to three times faster) than the hardware method. Another reason is that the Intel way of switching tasks isn't portable at all"
  32. ^ "news: Multitasking for x86 explained #1" (Article). NewOrer. NewOrder. May 2, 2004. Archived from = 10562 the original on 2007-02-12. Retrieved 2007-07-29. "...both rely on the Intel processors power to switch tasks, they rely on it in different ways."

External links

  • Protected Style Nuts
  • Introduction to Protected-Manner
  • Overview of the Protected Way Operations of the Intel Compages
  • Intel 64 and IA-32 Architectures Software Developer's Manuals
  • TurboIRC.COM tutorial to enter protected style from DOS
  • Protected Mode Overview and Tutorial
  • Code Project Protected Mode Tutorial
  • Akernelloader switching from real mode to protected mode

What Registers Can U Use With Real Mode 16 Bit,

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